Testing high performance silicon memory in a system-on-a-chip (“SoC”) integrated circuit at-speed in the gigahertz (“GHz”) range has shown to be problematic. Currently available test techniques have timing limitations produced by the built-in self-test (“BIST”) controller circuit.
As such, it is desirable to present a system and method for testing memory at-speed in the GHz range. In addition, other desirable features and characteristics will become apparent from the subsequent summary and detailed description, and the appended claims, taken in conjunction with the accompanying drawings and this background.